An integrated circuit is an interconnected ensemble of devices formed within a semiconductor material and within a dielectric material overlying a surface of the semiconductor material. Devices which may be formed within the semiconductor include MOS transistors, bipolar transistors, diodes, and diffused resistors. Devices which may be formed within the dielectric include wiring layers, thin film resistors, inductors and capacitors. The devices are interconnected by conductor paths formed within the dielectric. Typically, two or more levels of wiring, with successive levels separated by a dielectric layer containing connecting vias, are employed as interconnections. In current practice, copper and inorganic silicon oxide based dielectrics are commonly used for, respectively, the conductor and the dielectric materials.
In the manufacture of devices on a semiconductor wafer, it is common practice to fabricate multiple levels of conductive metal layers above a substrate. The multiple metallization layers are employed in order to accommodate higher densities as device dimensions shrink to deep sub-micron design rules. Likewise, the size of interconnect structures continues to shrink in order to accommodate the smaller dimensions.
Damascene metallization approaches have been employed to create inlaid metal structures, especially when utilizing copper interconnect metallization. In the single Damascene approach, the via dielectric is deposited and etched, then it is filled with metal (barrier and conductor) and planarized using chemical mechanical polishing (CMP) techniques. The trench dielectric is then deposited and patterned to allow deposition of the trench metallization, followed again by planarization. In a dual Damascene integration scheme, the via and trench structures are formed in the completed dielectric stack, then the metal is deposited in both structures at the same time.
The dual Damascene process offers an advantage in process simplification by reducing the process steps required to form the vias and trenches for a given metallization level. The openings for the wiring of a metallization level and the underlying via connecting the wiring to a lower metallization level are formed sequentially, prior to metal interconnect formation. The procedure provides an advantage in lithography and allows for improved critical dimension control. Subsequently, both the via and the trench can be filled utilizing the same metal-filling steps and planarized concurrently, thereby reducing the number of processing steps required.
For several technology generations, the typical integration approach for interconnect metallization has been the dual Damascene approach where a trench and a via are inlaid in a dielectric film stack, filled by a metal, and planarized using CMP to form an inlaid metal interconnect (see, for example, Zhao et al., U.S. Pat. No. 6,100,184). Dual Damascene patterning schemes can be categorized as “via first” or “trench first,” based on which pattern is etched first. Approaches have been the “trench over via—via first” integration (see, for example, R. H. Havemann and J. A. Hutchby in Proceedings of the IEEE 89, #5, pp. 586-601, 2001, and references therein) and the “metal hard-mask—trench first” integration (see, for example, J. Kriz et al. in Microelectronic Engineering, Vol. 85, #10, pp. 2128-2132, 2008, and references therein and also K. Hamioud et al. in Microelectronic Engineering Vol. 87, #3, pp. 316-320, 2010, and references therein).
Regardless of the integration scheme chosen, various dielectric materials may be chosen, driven by the requirements for the technology being implemented. Also, several different combinations of metal layers could be used to build the interconnect structure.
The combinations may include diffusion barrier materials deposited by PVD, CVD, or ALD techniques which typically contain nitrides of refractory metals. Materials such as ruthenium, cobalt or manganese could also be included in the metal stack. The conductors are typically copper, but could also contain other metals such as cobalt, aluminum, manganese, gold, silver, titanium, nickel, or alloys thereof. It has also become common to use a metal capping layer to reduce electromigration of fine interconnects. These layers are typically deposited using electroless deposition or a CVD deposition technique.
New approaches for patterning, etch, and metallization are required as existing approaches become inadequate at these small dimensions. The present disclosure seeks to extend Damascene technology to metallization half-pitches of 16 nm or less (pitches of 32 nm or less) in accordance with the ITRS. Dual Damascene technology, using various hard masks and multiple lithography and etch steps per layer, is becoming increasingly complicated and expensive. Moreover, the single step metallization used in dual Damascene integration necessitates line and via fill taking place together. Single step metallization can impose a burden on the metallization process because via processing may have different requirements from line processing. An approach separating via formation from the line formation could simplify processing while improving process control. One way to achieve separation is the single Damascene integration scheme. The approach has its own limitations, however. In particular, line alignment to via becomes difficult, since the two are formed at different levels. Cost is another disadvantage to the approach.
Metallization of narrow features poses a series of challenges. Keys among them are: patterning, gap fill, and reliability. The fine line width requirements are driving a need for new lithography methods, including double-patterning, which can improve the resolution in one axis, but not in both axes of the wafer plane. It is also becoming more difficult to execute steps such as pore-sealing of low dielectric constant materials after underlying metal layers are exposed, thereby reducing the choices for chemical treatment. Furthermore, it is becoming increasingly difficult to deal with topography during the lithography and etch sequence, while maintaining fine feature dimensions. Additionally, it is becoming more difficult to achieve void-free filling of narrow features with conductive metal. However, voids may have a tendency to migrate and coalesce under electrical stress. Indeed, the small features of the metal interconnects themselves tend to increase resistivity and the electromigration of the interconnect metal.
Therefore, there exists a need for an improved integration scheme not limited by the aforementioned problems. The present disclosure provides an alternative integration scheme to create features (such as trenches and vias, particularly in Damascene applications) of a microelectronic workpiece which does not suffer from the problems associated with conventional integration schemes.